FIG. 1 shows a traditional DC-to-DC converter 10 which comprises a control circuit 12 and four channels 14. Each channel 14 comprises transistors 1404 and 1406 connected in series between the input Vin and ground GND and a driver 1402 in response to the pulse width modulation signals PWM[1] to PWM[4] from the control circuit 12 to switch transistors 1404 and 1406 to regulate channel currents Io1 to Io4. The channel currents Io1 to Io4 are combined to be an output current Io for charging a capacitor C to generate an output voltage Vo. The control circuit 12 detects the channel currents Io1 to Io4 and output voltage Vo for modulating duty cycle of the transistors 1404 and 1406 in the channels 14.
FIG. 2 shows a traditional control circuit 12. A current sense circuit 1236 in a pulse width modulator 1201 senses the channel currents Io1 to Io4 to generate current sense signals Ix[1] to Ix[4] for sample and hold circuit 1238 to generate current sense signals Ix[1]′ to Ix[4]′. An adder 1240 in a voltage generator 1202 combines the current sense signals Ix[1]′ to Ix[4]′ to produce a summing current signal Isum. Since the output current Io is the summation of the channel currents Io1 to Io4 and the current sense signals Ix[1]′ to Ix[4]′ are proportional to the channel currents Io1 to Io4, respectively, therefore the summing current signal Isum is proportional to the output current Io. The summing current signal Isum flows through a pin ADJ to a resistor RADJ so as to produce a voltage VADJ which is thereby proportional to the output current Io. A digital-to-analog converter (DAC) converts a digital voltage VID[n:0] to an analog voltage VIA. A subtracter 1206 subtracts the voltage VADJ from the analogy voltage VIA to produce a reference voltage VREF. An error amplifier 1208 in the pulse width modulator 1201 provides an error signal VEA to a pin COMP in response to the feedback voltage VFB from a pin FB, which represents the output voltage Vo, and the reference voltage VREF. ARC network 16 is connected between the output Vo and the pin FB, and a compensation network 18 is connected between the pins COMP and FB. The ramp generators 1212, 1214, 1216, and 1218 generate ramp signals RAMP[1], RAMP[2], RAMP[3], and RAMP[4], respectively, in response to a clock CLK provided by an oscillator 1210. An adder 1220 uses the current sense signal Ix[1]′ to shift the level of the ramp signal RAMP[1] to generate a ramp signal RAMP[1]′. A comparator 1228 compares the error signal VEA with the ramp signal RAMP[1]′ to generate a pulse width modulation signal PWM[1]. An adder 1222 uses the current sense signal Ix[2]′ to shift the level of the ramp signal RAMP[2] to generate a ramp signal RAMP[2]′, and a comparator 1230 compares the error signal VEA with the ramp signal RAMP[2]′ to generate a pulse width modulation signal PWM[2]. An adder 1224 uses the current sense signal Ix[3]′ to shift the level of the ramp signal RAMP[3] to generate a ramp signal RAMP[3]′, and a comparator 1232 compares the error signal VEA with the ramp signal RAMP[3]′ to generate a pulse width modulation signal PWM[3]. An adder 1226 uses the current sense signal Ix[4]′ to shift the level of the ramp signal RAMP[4] to generate a ramp signal RAMP[4]′, and a comparator 1234 compares the error signal VEA with the ramp signal RAMP[4]′ to generate a pulse width modulation signal PWM[4].
FIG. 3 is a waveform diagram to show several signals of the DC to DC converter 10 in a load transient, in which waveform 20 represents the load current IRL flowing through the load RL, waveform 22 represents the output current Io, waveform 24 represents the voltage VADJ, waveform 26 represents the reference voltage VREF, waveform 28 represents the DC value Vo,avg of the output voltage Vo, and waveform 29 represents the clock CLK. In DC condition, the impedance device 18 in the DC-to-DC converter 10 is open circuit, and the voltage Vo equals to the feedback voltage VFB. Hence the waveform 26 of the reference voltage VREF and the waveform 28 of the voltage Vo,avg are shown together in FIG. 4. Referring to FIGS. 1 to 4, in the load transient of from light loading to heavy loading, the current IRL which flows through the load RL rises up quickly, as shown by the waveform 20, and the voltage Vo,avg drops down quickly as shown by the waveform 28. However, the output current Io can't rise up as fast as the current IRL, whose rising speed is slower, as shown by the waveform 22. Since the voltage VADJ is proportional to the output current Io, the voltage VADJ rises up slowly as the output current Io. Due to the reference voltage VREF equal to (VIA−VADJ), the falling speed of the reference voltage VREF is slower than the voltage Vo,avg, as shown in FIG. 4. Since the falling speed of the voltage Vo,avg is faster than the reference voltage VREF in load transient, and the feedback voltage VFB will always trace to the reference voltage VREF in the DC-to-DC converter 10, and when the converter 10 reaches stable, the voltage Vo,avg will be equal to the feedback voltage VFB, therefore the voltage Vo,avg will also follow the reference voltage VREF. When the voltage Vo,avg drops to the predetermined value V1, the reference voltage VREF does not reach the value V1 yet, as shown in FIG. 4, and therefore the voltage Vo,avg will rise to follow the reference voltage VREF. After the voltage Vo,avg reaches the reference voltage VREF, it will drop slower to level V1 as the decreasing reference voltage VREF. As a result, a ringback is produced. The ringback will affect the performance of the load circuit, which is connected to the output Vo of the DC-to-DC converter 10, for example CPU. In addition, during the load transient period T, since the falling speed of the voltage Vo,avg is faster, it could result in undershoot. In other words, the voltage Vo,avg maybe drop to a value V2 which is lower than the predetermine value V1, as shown in FIG. 4. It also affects the performance of the load circuit.
Therefore, it is desired a control circuit for improving the ringback and undershoot of a DC-to-DC converter during the load transient.